Meeting schedules

By Vorachet Jaroensawas
Future Events Listing

Meeting schedule calls (Sep - Aug)
http://thaisysml.blogspot.com/2015/07/meeting-schedule-calls-sep-aug.html

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Simple Clock Modeling with SysML

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It has been a while since I posted my previous article on this blog, because I was busy in making MagicDraw SysML supports for the new OMG SysML v1.3 Specification [1]. Couple weeks ago, I was asked by a customer about how to model a clock which counts every second with SysML. I created the simple clock model for answering. I also posted it to the SysMLForum and found that some people are interested in my clock model. So, I wrote this article to explain about the clock model and show how to model the system operating by a time trigger. Start from defining the clock with a SysML block. The clock block contains only a value property t . This value property represents time in second. Thus, a value type Second must be defined for typing the value property as in Figure 1. Figure 1 - SysML Block Definition Diagram of Clock Model Next, SysML State Machine will be created to describe the behavior of the clock block. Here, the clock state-machine was designed to have only ...
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Re-activating the SysML Users in Thailand and changed the name to "MBSE Thailand"

By Vorachet Jaroensawas
11 October 2024 Hi everyone, I’ve recently received several emails from people who still believe this site is actively maintained by users in Thailand. In reality, we stopped managing the site back in 2017. However, after seeing the ongoing interest—especially regarding Systems Modeling Language (SysML) v2. I feel it’s time to revive this community. It’s clear there’s still a dedicated user base in Thailand, and I’m excited about re-engaging with all of you. To further enhance this experience, we are also taking this opportunity to create space on the same platform for Capella users. By including both SysML v2 and Capella, we aim to maximize the learning experience, allowing Thai learners and professionals to benefit from widely-used languages in the systems engineering industry. Whether you’re passionate about SysML v2, Capella, or both, I encourage you to get involved. Let’s collaborate, share knowledge, and create a thriving space for everyone interested in advancing their skills in...
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A Common Misunderstanding in Using Connectors

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I have been asked many times by customers, that why they cannot use a connector to connect between ports on the boundaries of blocks in SysML Block Definition Diagram (BDD). Is that a tool's problem? After I have answered this question many times, I think it would be helpful for SysML users if there is an article to answer such question. For easy to explain, please see Figure 1. My customers try to use a connector to connect port p1  of SubSystem1 to the port p2  of SubSystem2  but they cannot. So, they have asked me with above question. Figure 1 -- SysML Block Definition Diagram To answer it, we should start by asking ourselves that does it make sense if a connector can connect both ports together? What should be the meaning of that connection? especially when we have multiple instances of SubSystem1 and SubSystem2 . Should the ports p1 of all  SubSystem1  instances be connected to the ports p2 of all  SubSystem2  ...
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