It has been a while since I posted my previous article on this blog, because I was busy in making MagicDraw SysML supports for the new OMG SysML v1.3 Specification [1]. Couple weeks ago, I was asked by a customer about how to model a clock which counts every second with SysML. I created the simple clock model for answering. I also posted it to the SysMLForum and found that some people are interested in my clock model. So, I wrote this article to explain about the clock model and show how to model the system operating by a time trigger. Start from defining the clock with a SysML block. The clock block contains only a value property t . This value property represents time in second. Thus, a value type Second must be defined for typing the value property as in Figure 1. Figure 1 - SysML Block Definition Diagram of Clock Model Next, SysML State Machine will be created to describe the behavior of the clock block. Here, the clock state-machine was designed to have only one state
