About us

By Vorachet Jaroensawas
The SysML & Capella Users Group in Thailand fosters the exchange of information among its members. Through sharing their knowledge and experiences, they enhance their understanding of the language, methods, and tools associated with SysML and Capella.

Keep in mind that modeling language can be creatively beneficial when applied effectively. Systems engineering offers various methods for tackling problem-solving activities. SysML and Capella are excellent tools for communicating system design and modeling complex systems. However, we also have numerical methods and various techniques in systems thinking.To maximize your benefits, keep learning in SE and explore various SE tools, as they are crucial for real-world R&D in complex projects. 

Purpose
  • To develop an open forum that provides real-world value to members, volunteers, and sponsors.
Contact 

For more information about becoming a sponsor, a workshop sponsor, and an article writer,  please contact vorachet@gmail.com 




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Simple Clock Modeling with SysML

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It has been a while since I posted my previous article on this blog, because I was busy in making MagicDraw SysML supports for the new OMG SysML v1.3 Specification [1]. Couple weeks ago, I was asked by a customer about how to model a clock which counts every second with SysML. I created the simple clock model for answering. I also posted it to the SysMLForum and found that some people are interested in my clock model. So, I wrote this article to explain about the clock model and show how to model the system operating by a time trigger. Start from defining the clock with a SysML block. The clock block contains only a value property t . This value property represents time in second. Thus, a value type Second must be defined for typing the value property as in Figure 1. Figure 1 - SysML Block Definition Diagram of Clock Model Next, SysML State Machine will be created to describe the behavior of the clock block. Here, the clock state-machine was designed to have only ...
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Decomposing Ports and Connectors with Association Blocks

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This article was written when SysML v1.3 specification is in releasing process. If you are a big fan of SysML and keep in touch with SysML RTF, you may have seen some documents or books about SysML v1.3 such as [1] and [2]. One of many things that I am impressed in those books and documents, is the way they use SysML to describe nested ports and specify compatibility between connected ports using association blocks.  When two ports connected by a connector, they may have nested ports which themselves can be connected. An association block has been suggested for defining the internal structure of the connector. It could contain a set of connectors that define the connectors between nested ports of association ends. When a connector is typed by an association block, the interaction between roles at both ends of connector will be handled by the internal structure of the association block [1].  This approach give us not only the ability to decompose ports and connectors ...
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A Common Misunderstanding in Using Connectors

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I have been asked many times by customers, that why they cannot use a connector to connect between ports on the boundaries of blocks in SysML Block Definition Diagram (BDD). Is that a tool's problem? After I have answered this question many times, I think it would be helpful for SysML users if there is an article to answer such question. For easy to explain, please see Figure 1. My customers try to use a connector to connect port p1  of SubSystem1 to the port p2  of SubSystem2  but they cannot. So, they have asked me with above question. Figure 1 -- SysML Block Definition Diagram To answer it, we should start by asking ourselves that does it make sense if a connector can connect both ports together? What should be the meaning of that connection? especially when we have multiple instances of SubSystem1 and SubSystem2 . Should the ports p1 of all  SubSystem1  instances be connected to the ports p2 of all  SubSystem2  ...
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